This invention relates to a pattern generator and in particular to a pattern generator which is suitable for generating patterns having an operating function with a high speed.
A prior art pattern generator was an IC test equipment, which is, as described in JP-A-54-12657 as a pattern generator e.g. for an IC test equipment, so constructed that N pattern generators, whose outputs are taken out sequentially, are disposed and they effect pattern generation with a speed N times as high as that of the individual pattern generator as a whole. In this case if the tested IC is a logic IC tested with a test pattern, which has no algorithmic property and is called random pattern, the individual pattern generator is usually constructed with a memory, which stores the test pattern itself, and a relatively simple control logic circuit, which reads out the test pattern, and it seems that it can be easily realized to speed up its operation by parallel read, as described in the publication stated above.
However, in the case where the tested IC is a memory, an algorithmic pattern generator (hereinbelow abbreviated to ALPG) of microprogrammed architecture having an operating function is used as the pattern generator, but parallel operation of N ALPGs cannot be realized by simply connecting N identical ALPGs, because parallel operations, which are totally independent of each other, as performed by an array processor effecting vector operations, are not possible, and also because dummy cycles coming from the particularity that it is a test pattern is not allowed, and such a hardware construction and parallel program techniques, which the prior art computer techniques have not, are inevitable. This fact is not taken into account in the techniques disclosed in the publication stated above.
FIG. 13 shows an approximate construction of a prior art memory IC test equipment. In this equipment a timing generator 3 generates signals such as a rate clock signal determining a test cycle, a phase signal determining a point within the test cycle at which a test signal waveform should be given to a memory T2 to be tested, etc. On the other hand, a pattern generator 2 receives the rate clock signal 4 coming from the timing generator 3, carries out a test program within the pattern generator 2 for every test cycle in synchronism with the rate clock signal 4 and generates various sorts of test patterns. This test program is, in general, sent from the computer 1 to the pattern generator 2 to be carried out therein, after a development or debug of the test program has been carried out in the computer 1 a test system.
Pattern data 5 coming from the pattern generator 2 consist of data applied to the memory under test T.sub.2 such as address data, data to be written, read/write control data, etc. and an expected value 6, which is to be compared with read out data.
A fail memory T5 stores judgment result GO/NG obtained on the basis of a judgment stroke signal given by the timing generator 3 to the comparator, which result is transferred to the computer, after having carried out a test, to be subjected there to a defect analysis operation.
FIG. 14 shows the approximate internal construction of the pattern generator 2 in FIG. 13, which consists roughly of a sequence control unit 7 and a data operating unit 8. The sequence control unit 7 has a microprogramed architucture, as indicated in the figure and consists of an instruction memory 9, in which microprograms are stored, a program counter 10 deciding the read address 14 therefor, a multiplexer 11, which changes over the branch address 13 generated during the execution of the program, the program execution starting address specified by the computer 1, etc., and an instruction decoder 101, which decodes the content of the program for generating a load signal 120, which takes-in a new address into the program counter at the moment of branching, etc. and in addition an interruption control signal 111 to the computer 1, etc.
Further, as indicated in FIG. 14, a register 100 storing instruction data 15 coming from the instruction memory 9 generates a branch address signal 13 to the multiplexer 11, a read/write control signal 110 to the memory under test T2 and instruction data 112 to the instruction decoder 101.
The data operating unit 8 carries out arithmetic operations such as addition, subtraction, etc. and logic operations 0/1 inversion, bit shift, etc. according to the instruction data 15 coming from the instruction memory 9 in the sequence control unit 7, and outputs an algorithmic pattern.
In this way the ALPG has a feedback loop made of a hardware for the branch address 13, a load signal to the program counter 10, etc. in order to realize operations including branch operations, such as loops and repeats according to the program, by itself. For this reason, as a method similar to that disclosed in the publication stated previously to increase the speed by disposing a plurality of low speed memories, in which the test pattern is stored, in parallel, a method may be proposed, by which a plurality of ALPGs indicated in FIG. 13 are disposed in parallel. However, as a test equipment for one pattern generator indicated in FIG. 13, it is impossible to use a plurality of test programs (microprograms) 12 connected in parallel as they are. This will be explained below by using a program for memory test pattern generation called galloping indicated in FIGS. 15 and 16.
FIG. 15 illustrates the content of the microprogram for galloping pattern generation together with the flow chart therefor, in the case where the capacity of the memory under test n is 32 bits.
(1) Clear all the cells of the memory under test by means if a loop L1, which is repeated 32 times.
(2) Choose one of the cleared memory cells as the test cell and write data "1" in that memory address (A=address i).
(3) Read out the data at the address (A=address i+j) in the neighborhood of the test cell as a disturb cell and check it.
(4) Read out the test cell address (A=address i) and examine influences of the access to the distrub cell.
(5) Judge whether the access of the remaining 31 bits except for the test cell as the disturb cell is terminated after having read out again the disturb cell address (A=address i+j) and examined it, and if it is not terminated, return to the processing step (3) through a loop L2. Repeat (3)-(4)-(5).
(6) Write data "0" in the test cell address to clear it after having read out all the remaining cells as the disturb cells for one test cell. Then, judge whether the read out and examination described above are completed by using all the cells as test cells. If it is not completed, add 1 (i=i+1) to the present test cell address (A=address i) and return to the processing step (2) through a loop L3. The program of the galloping pattern in FIG. 15 is terminated and the flow is ended, after the examination has been completed for the test cells by executing the processings (2)-(6). However, precisely speaking, the galloping pattern is terminated by executing the processings (1)-(6) in the form, where the data "0" and "1" are inverted, called inverse pattern examination, but this is omitted. In this way even a long test pattern called n.sup.2 sequence can be expressed by a program statement of only several lines having a loop structure as indicated in FIG. 15, by utilizing the regularity of its generating pattern.
FIG. 16 shows the possibility of the parallel execution, by which two ALPGs (I) and (II) are assigned alternatively to the steps of programs having a same content, for which the flow chart is represented schematically in FIG. 15. As the result, for all the three loops L1, L2 and L3 indicated in FIG. 16, the ALPG, which is in charge of the step at the starting point of the returning loop, and the ALPG, which is in charge of the step at the destination of the returning loop are always same and thus it is impossible to increase the speed by the alternative operation of the two ALPGs as they are, when the program in this figure is carried out.
That is, the loop L1 in FIG. 16 is a repetition of a same step, in which the ALPG (I) operates alone, and the alternative execution of the ALPGs (I) and (II) is impossible. The loop L2 represents a repeated execution including the return from step (5) to step (3) and the steps (3), (4) and (5) are executed alternatively one after another by (I), (II) and (I), respectively, but at the return of the loop L2 from step (5) to step (3), since the same ALPG (1) must execute two successive steps, the parallel execution is impossible. Further, it can be seen that also for the loop L3, at the execution of the return of the loop the ALPG assigned to (6) and (2) is always (II) and therefore two different ALPGs cannot be assigned thereto.
On the other hand, at each step of the program indicated in FIG. 16 the address calculation as indicated in FIG. 15 is performed. Consequently, in order that two ALPGs can perform a program alternatively, as indicated above, it is necessary that one of the ALPGs performs operations after having known the result of operations obtained by the other. In the prior art ALPG system this was not taken into account and also for the address calculation the parallel execution processing was not possible.
As explained above, a test program formed for an IC test equipment constructed by one ALPG cannot be applied to any IC test equipment constructed by N parallel ALPGs for the purpose of increasing the speed. A new measure therefor was absolutely necessitated.